1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an ESD protection circuit, of which the parasitic BJT can be turned on in advance by triggering a substrate under ESD stress conditions, so that the ESD capacity can be enhanced.
2. Description of the Related Art
Electrostatic discharge (ESD) can easily damage IC devices such as DRAMs and SRAMs during both manufacture and operation. A person walking on a carpet, for instance, can carry up to several thousand volts of electrostatic charge under high relative humidity (RH) conditions and over 10,000 volts under low RH conditions. If such a person touches an IC package, the electrostatic charge on his/her body is instantly discharged to the IC package, thus causing ESD damage to the internal circuitry of the IC package. A widely used solution to this problem is to provide an on-chip ESD protection circuit around each I/O pad of the IC package.
One drawback to the prior art, however, is that when the IC device is fabricated by scaled down technology, such as the deep-submicron CMOS process, the gate-oxide structure is reduced in thickness. This causes the breakdown voltage of the gate-oxide structure to be close to or below the breakdown voltage at the source/drain junction, thus degrading the ESD protection capability. The internal circuitry of an IC device is typically drawn in accordance with the Minimum Design Rules. Therefore, the various semiconductor components of an IC device are designed to have the minimum size. This practice, however, makes some components vulnerable to ESD stress when these components are further scaled down. For this reason, a highly integrated IC device fabricated by deep-submicron process is particularly vulnerable to ESD. Therefore, in the IC industry, much research effort has been directed to ESD protection for integrated circuitry.
FIG. 1 is a circuit diagram for a conventional ESD protection circuit. As shown in FIG. 1, in order to protect the internal circuit 16, the ESD current imported through an input/output (I/O) pad 10 can be discharged not only through an NMOS transistor 12 to the ground VSS but also through a PMOS transistor 14 to a voltage source VDD.
The conventional ESD protection circuits as described above and shown in FIG. 1 utilizes junction breakdown voltage to protect the internal circuit 16 from damage. In order to protect internal circuit 16, the conventional operation method utilizes a parasitic bipolar device to discharge the ESD current imported through the I/O pad 10, that is, the conventional method utilizes hole current (electron current) generated by drain junction avalanche breakdown to trigger a P-N junction (that is, trigger a parasitic BJT to turn on) between substrate and source of NMOS transistor 12 (or PMOS transistor 14) to turn on.
However, whether the P-N junction between substrate and source is easily turned on has a direct effect on the ESD protection circuit capability. Thus, in the future development for ESD protection circuit, this is a key technology for how to advanced turn on parasitic BJT in ESD stress condition so as to enhance the internal circuit protection capability.
In addition, when the IC device is fabricated by a scaled down CMOS process and the gate-oxide structure is accordingly reduced in thickness, some problems arise; for example, the breakdown voltage of the gate-oxide structure happens earlier than the junction breakdown voltage at the source/drain junction. In other words, if the breakdown voltage of the gate-oxide structure happens earlier than the junction breakdown voltage at the source/drain junction, then the conventional ESD protection circuits shown in FIG. 1 lose their protective ability.